Technical Field
The present disclosure relates generally to voltage regulators, and more specifically to supply voltage rejection (SVR) in voltage regulators.
Description of the Related Art
Supply voltage rejection (SVR) is one of the most important parameters utilized to characterize the performance of a voltage regulator. A voltage regulator receives an input or supply voltage and generates a controlled or regulated output voltage having an approximately constant value independent of variations in the supply voltage. Variations in the value of the supply voltage may be present because of an alternating component or noise signal present on the supply voltage. This noise signal or simply “noise” may be caused by a variety of factors, such as switching of components in electronic circuitry coupled to or positioned proximate the regulator. The SVR of the voltage regulator indicates the ability of the voltage regulator to suppress this noise such that these variations are not present on the output voltage of the regulator. SVR is typically measured in decibels on a logarithmic scale utilizing the ratio of the variations in the output voltage divided by variations in the input voltage.
As will be appreciated by those skilled in the art, the SVR of a voltage regulator is a frequency dependent parameter having characteristics determined by the type of circuitry utilized in forming the voltage regulator as well as the physical layout of this circuitry. The SVR typically worsens as frequency increases and is influenced by parasitic components in the voltage regulator, which are present in all electronic circuits. This is true because as the frequency of the noise on the input increases, more of this noise is coupled to the output of the regulator through these parasitic components, degrading the SVR of the regulator.
Where the voltage regulator is formed in an integrated circuit, the distances between components forming the regulator may be extremely small, resulting in parasitic elements, particularly capacitive parasitic elements, having significant values that may adversely affect the SVR of the voltage regulator. For example, conductive layers separated by extremely thin interlayer dielectrics may result in parasitic capacitances in the femtofarad range. While femtofarad parasitic capacitances have extremely small values in absolute terms, the reactance values and resulting capacitive coupling introduced by such parasitic capacitances can be significant in the frequency operating ranges of modern integrated circuits, particularly in the Megahertz and Gigahertz frequency ranges. This unwanted capacitive coupling lowers the SVR of the voltage regulator, which is of course undesirable. As the frequency of operation increases, the capacitive coupling of these parasitic capacitances increases, as will be appreciated by those skilled in the art.
No matter how the circuitry of a voltage regulator is physically arranged in the integrated circuit or the particular materials used for forming such circuitry, parasitic capacitances and the associated undesirable parasitic coupling effects cannot be completely avoided or eliminated. Typically, layout modifications are made and shielding used to reduce the adverse effects of parasitic capacitances on the SVR of a voltage regulator. There is a need for improved approaches to achieve desired levels of SVR where such layout modifications and shielding do not yield the desired performance.